1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device and, particularly, to a non-volatile semiconductor memory device including a sense amplifier, for detecting and outputting data held in a memory cell, and a latch circuit, for latching an output of the sense amplifier, and performing a read operation at a high source voltage during a verify mode.
2. Description of the Related Art
A non-volatile semiconductor memory device is usually constructed with a memory cell array composed of a plurality of non-volatile memory cells each comprising a non-volatile memory cell MOSFET and a peripheral circuit for selecting one of the memory cells according to an input address and writing or reading the selected memory cell. The memory cell MOSFET includes a floating gate and a control gate, and stores data by charge accumulation in the floating gate. To write or program data in the memory cell MOSFET, a so-called programming voltage is used to accumulate charge to be stored in the floating gate. The memory cell MOSFET thus programmed has a threshold voltage higher than that of a non-programmed MOSFET.
The non-volatile semiconductor memory device constructed as mentioned above has a special mode called the "verify mode". The verify mode is a mode in which, immediately after data is written in a predetermined memory cell corresponding to an input address, the data is read from the same memory cell to confirm that the data is actually written in the memory cell. To this end a verifying voltage is applied to the control gate of that memory cell MOSFET and a sense amplifier is activated to detect the data actually written in the memory cell. If the memory cell is actually programmed, it maintains a non-conductive state against the verifying voltage supplied to the control gate thereof. If not, the memory cell MOSFET is rendered conductive by the verifying voltage. Thus, the verify mode is similar to a "read mode" in which data stored in a selected memory cell is read out therefrom by applying a reading-out voltage to the control gate of the selected memory cell. Needless to say, the programmed memory cell MOSFET is required not to be turned on by the reading-out voltage in the read mode. To this end, the verifying voltage, which is higher in potential level than the reading-out voltage, is applied to the memory cell MOSFET in the verify mode to confirm the programmed memory cell MOSFET is not turned on against such a relative high gate voltage.
As well known in the art, each of the reading-out voltage and the verifying voltage is derived from a power source voltage applied to the memory device and further has a potential level substantially equal to the power source voltage. That is, the power source voltage applied during the verify mode is higher than the power source voltage applied during the read mode. In a typical case, the power source voltage during the verify mode is 6.5 V, whereas the power source voltage during the read mode is in a range of 4.5-5.5 V.
Thus, a data read operation is performed in the verify mode in condition of receiving a relatively large power source voltage. This means that the charging and/or discharging of digit lines in the memory cell array is performed with the large power source voltage. In other words, a relatively large charging and discharging currents flow and cause the occurrence of large noise on the power source lines. For this reason, there is a possibility that the sense amplifier temporarily outputs an erroneous data due to the large noise. The output of the sense amplifier is latched by a latch circuit at a predetermined timing. Therefore, such erroneous data may be latched in the latch circuit. As a result, the data read is verified as if the erroneous data was written in the memory cell.